1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device in which a non-volatile semiconductor memory, such as a flash memory, and a standard semiconductor device of MOS-type are formed on the same substrate.
2. Description of the Related Art
Hereinafter, a conventional method for manufacturing a semiconductor device provided with a non-volatile semiconductor memory and a semiconductor device will be described with reference to the drawings. FIGS. 8A to 12B are cross-sectional views illustrating the steps in a conventional method for manufacturing the semiconductor device. In FIGS. 8A to 12B, a region where the non-volatile semiconductor memory is to be formed is indicated as a memory region Rmem and a region where the standard semiconductor device is to be formed is indicated as a logic region Rlogic.
First, as shown in FIG. 8A, an insulating film 2, for separating the non-volatile semiconductor memory and the semiconductor device, and a p-well 3 are formed on a p-type silicon substrate 1. Next, a first insulating film 4, a first polysilicon film 5, and a second insulating film 6 are formed in an active region of the p-type silicon substrate 1 successively.
Then, as shown in FIG. 8B, using a resist pattern 7 as a mask, the second insulating film 6 and the first polysilicon film 5 on the logic region Rlogic are removed by etching.
Further, as shown in FIG. 8C, a third insulating film 8 is formed by oxidizing the substrate surface in the logic region Rlogic. Thereafter, a second polysilicon film 9 is formed. The thickness of the second polysilicon film 9 at this time is about 200 nm, for example.
In general, the second insulating film 6 has a three-layer structure including a silicon oxide film/silicon nitride film (Si3N4)/silicon oxide film, although this structure is not specifically illustrated in the drawings. The silicon oxide film at the top of the second insulating film 6 is formed by the thermal oxidation performed when forming the third insulating film 8 in the logic region Rlogic.
Subsequently, as shown in FIG. 9A, the second polysilicon film 9, the second insulating film 6, the first polysilicon film 5, and the first insulating film 4 in the memory region Rmem are etched using a resist pattern 10 as a mask. As a result, a control gate electrode 9a, a capacitor insulating film 6a, a floating gate electrode 5a, and a tunnel insulating film 4a are formed, respectively.
Then, as shown in FIG. 9B, a silicon oxide film 11 is formed on the entire surface of the p-type silicon substrate 1 by chemical vapor deposition (CVD) or thermal oxidation. The thickness of the silicon oxide film 11 at this time is about 20 nm, for example.
Next, as shown in FIG. 9C, using a resist pattern 12 as a mask, ion implantation 13 is performed for forming a source of the non-volatile semiconductor memory. As a result, a high concentration source region 14 is formed.
After that, as shown in FIG. 10A, using a resist pattern 15 as a mask, ion implantation 16 is performed for forming a drain of the non-volatile semiconductor memory. As a result, a high concentration drain region 17 is formed. The silicon oxide film 11 has been formed so that it can serve as a protective oxide film for preventing the tunnel insulating film 4a and capacitor insulating film 6a from being damaged by the ion implantations for forming the source and the drain of the non-volatile semiconductor memory on the side faces of the gate electrode of the non-volatile semiconductor memory.
The silicon oxide film 11 is then removed by etching as shown in FIG. 10B. After that, a resist pattern 18 for forming a gate electrode of the semiconductor device in the logic region Rlogic is formed as shown in FIG. 10C.
Subsequently, as shown in FIG. 11A, the second polysilicon film 9 in the logic region Rlogic is etched using the resist pattern 18 as a mask. As a result, a gate electrode 9b of the semiconductor device is formed. After that, the resist pattern 18 is removed. Then, using another resist pattern (not shown) that exposes the logic region Rlogic, ion implantation for forming a low concentration drain region 32 and a low concentration source region 33 is performed in the logic region Rlogic. After that, this resist pattern is removed. This brings about the state as shown in FIG. 11B.
Next, as shown in FIG. 12A, a silicon oxide film 21 as an insulating material is formed on the entire surface of the p-type silicon substrate 1 by CVD so that source and drain regions of the semiconductor device in the logic region Rlogic to be formed later will have an LDD structure.
Thereafter, as shown in FIG. 12B, the silicon oxide film 21 is etched by anisotropic etching until the upper face of a first gate 19 (see FIG. 11B) in the memory region Rmem and the upper face of a second gate 20 (see FIG. 11B) in the logic region Rlogic are exposed. As a result, a side-wall oxide film 22 made of silicon oxide film 21 is formed on the side walls of the first gate 19 and the second gate 20. After that, the semiconductor device in the logic region Rlogic is subjected to necessary ion implantations (for forming a high concentration source region 35 and a high concentration drain region 34) and wiring (not shown) to obtain a desired semiconductor device.
However, in the above-mentioned conventional method for manufacturing a semiconductor device, with the miniaturization of elements used in the semiconductor device, new problems arise as follows.
The first problem is as follows. The thickness of the resist pattern 18 shown in FIG. 10C has been made thinner in order to form a minute pattern. For example, when forming a pattern of 0.25 xcexcm or less by photolithography using a KrF excimer laser, the thickness of the resist pattern 18 is in a range from 0.5 to 0.7 xcexcm.
In this case, as shown in FIG. 10C, since the logic region Rlogic substantially is flat, the thickness of the resist pattern 18 formed by photolithography can remain in a range from 0.5 to 0.7 xcexcm in the logic region Rlogic. In contrast, in the memory region Rmem, the resist pattern 18 cannot have a uniform thickness since the laminated-type gate electrode pattern already has been formed. The resist pattern 18 has a small thickness, particularly above the gate electrode pattern.
Further, as shown in FIG. 11A, the second polysilicon film 9 is etched by dry etching using the above-mentioned resist pattern 18 as a mask. However, during the etching, since the selective ratio of the polysilicon film to the resist pattern generally is low, the resist pattern covering the electrode pattern in the memory region Rmem is removed before the etching of the gate electrode pattern in the logic region Rlogic is completed. Accordingly, although the etching step as a whole is not yet completed, the electrode pattern itself is exposed in the memory region Rmem. This leads to a problem that the control gate electrode 9a included in the electrode pattern in the memory region Rmem is etched to have an abnormal shape, resulting in a defective pattern.
The second problem is as follows. In the logic region Rlogic, the second gate of the semiconductor device is formed and the ion implantation for forming the low concentration drain region 32 is performed, as shown in FIGS. 11A and 11B. However, in a series of steps in which the formation of the resist pattern and the removal thereof are repeated, since a cleaning step is performed every time after the formation or the removal is completed, the surface of the high concentration source region 14 and the surface of the high concentration drain region 17 may be worn away by these cleaning steps. This may reduce the current flowing though the non-volatile semiconductor memory and interfere with a stable supply of current in the non-volatile semiconductor memory.
Therefore, with the foregoing in mind, it is an object of the present invention to provide a method for forming a semiconductor device that allows a desirable semiconductor device to be obtained by preventing, when patterning a gate electrode of a semiconductor device, a gate electrode of a non-volatile semiconductor memory that has been already patterned from having an abnormal shape and reducing the chances that the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory may be worn away to cause reduction and fluctuation in a transistor current.
In order to achieve the above-mentioned object, a method for forming a semiconductor device according to the present invention includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate. It is to be noted here that some etching of the protective film may be tolerated, as long as the protective film has a high resistance to the etchant.
According to this configuration, when patterning the gate electrode of the semiconductor device, the gate electrode of the non-volatile semiconductor memory that has been already patterned is prevented from being removed further by etching. Accordingly, the gate electrode of the non-volatile semiconductor memory is prevented from being formed in an abnormal shape, thus allowing the semiconductor device having a normal shape to be obtained.
Further, in the method for forming a semiconductor device according to the present invention, it is preferable that a height of the first gate is at least 200 nm greater than that of the second gate.
Furthermore, in the method for forming a semiconductor device according to the present invention, it is preferable that the protective film is a photosensitive resin film that has been cured.
Still further, in the method for forming a semiconductor device according to the present invention, it is preferable that a source region and a drain region of the non-volatile semiconductor memory are covered with the protective film when a mask material that has been used for patterning the second gate is removed.
According to the above-mentioned preferable configurations, it becomes possible to reduce the chances that the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory may be worn away to cause reduction and fluctuation in a transistor current.
Further, in the method for forming a semiconductor device according to the present invention, it is preferable that the protective film is one film selected from a silicon oxide film, a silicon nitride film, and a silicon oxynitride film, or a multilayer film including two or more of these films.
Furthermore, in the method for forming a semiconductor device according to the present invention, it is preferable that the protective film is formed by chemical vapor deposition.
Still further, in the method for forming a semiconductor device according to the present invention, it is preferable that the protective film is a silicon oxide film formed by thermal oxidation.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.